The IEEE 1394-1995 standard (also popularly known as "Firewire" .RTM.) describes a high speed, low cost serial bus to which compatible devices can be connected (even hot plugged) and automatically recognized. Although a detailed description of the 1394 standard will not be provided herein, an overview of certain aspects of bus and node architecture will be presented to aid in understanding the present invention.
1394 Bus Overview
FIG. 1 illustrates the basic physical topology of the bus. A 1394-compatible device 100, such as a computer, may include a serial bus backplane 102 to which internal devices, such as CPU 104, memory 106 and input/output interface 108 are connected. The backplane 102 is connected to a serial bus cable 110 through a bridge 112. The cable 110 is connected to ports on an additional, stand-alone 1394-compatible device 140, such as a hard disk drive, which in turn is daisy-chained to other devices 142, 144, 146, 148, 150, and 152. It will be understood that, one of the advantages of the 1394 environment is that any compatible device can be connected to a port on any other compatible device and in any order, with multi-port interfaces (such as that on the stand-alone CPU 142) repeating signals received in one port through to each other port: data can be transmitted from any device on the bus to any other device. Consequently, the specific configuration shown in FIG. 1 is for illustrative purposes only.
Each device connected to the 1394 bus is a uniquely identifiable node with an assigned logical address. When a node is connected to the bus, the bus is automatically re-initialized, clearing topology information stored in each node. Thereafter, one node is designated as the "root" node and the other nodes designated as "branches" or "leaves", thereby describing a "tree". Two nodes which are directly connected to each other are also described in parent/child terms, with the parent being closer to the root. Next, each node selects a unique ID and sends the identity information to all other connected nodes which store a table of the node IDs and their respective characteristics (including, for example, the maximum transmission/reception speed of each node). With such information, each node is able to target a particular node to a receive data packet.
When a data packet is to be sent from one node to another, the sending node begins to arbitrate on the bus by sending a request to its parent which forwards the request to its parent (if it is not the root) while denying bus access to later-received requests from any other of its children. The request is forwarded up the tree, child to parent, until it arrives at the root node which denies bus access to later-received requests from any of its other children. The root then grants access to the node which won the arbitration and all denied requests are withdrawn. The sending node alerts all other nodes that data is about to be sent and the data packet is transmitted onto the bus, addressed to the target node. Each node receives the packet and repeats it through its other ports and the packet eventually reaches the target node. The arbitration method just described, while ensuring that only one node at a time can transmit data, is biased in favor of the requesting node which is closest to the root. In order to allow more remote requesting nodes equal access to the bus, a fairness protocol is implemented when a requesting note sets its arbitration flag.
Node Overview
FIG. 2 is a simplified block diagram of a conventional 1394 node 200 comprising a transaction layer 202, a link layer 204, a physical layer 206 (more commonly referred to as a "PHY") and a serial bus manager 210. Briefly, the transaction layer 202 defines certain high level functions, such as how data is transferred between a node (e.g., a disk drive) and another node (e.g., a host computer) and how errors are handled. The link layer 204 communicates with the transaction layer 202 and provides addressing, data checking and data framing for packet transmission/reception. The PHY 206 translates signals from the link layer 204 into appropriate electrical signals for the 1394 bus, connected through ports 208, prevents more than one node from sending data by providing arbitration for the bus, and provides the physical interface between the node and the bus itself. The serial bus manager 210 provides functions to control nodes and manage bus resources; only one bus manager on the bus is active and exercises management functions for the entire bus.
FIG. 3 illustrates a typical arrangement of 1394-related components in a desktop computer 300 having an internal 1394 device, such as a hard disk drive 302, and external 1394 connector ports 304 for connection with a number of peripheral devices; a video-cable set-top box or notebook computer might have only a single external 1394 port. The computer 300 also includes a motherboard 306 with integrated link and transaction layers and a PHY chip 308 (while the link and transaction layers may be integrated into other chips, the PHY layer is generally implemented as a discrete chip). The PHY chip 308 is cable-connected both to the external 1394 ports 304 and to a PHY layer 310 in the disk drive 302 (which contains its own link and transaction layers and other requisite logic).